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Explain directives used in assembly language program ?

Explain directives used in assembly language program ? 

       Assumbler directories : Assumbler directives are statements which give direction to the assembler to perform the task of assembly process. These are not translated into machine code.

        Commonly used assembler directive in 8086 assembly language programming are explained below :
(i) ASSUME : The assume directive is used to tell the assembler the name of the logical segment it should used for a specified segment. The statement ASSUME CS:CODE for example tells the assembler that the instructions for a program are in a logical segment named CODE. The statement ASSUME DS: DATA tells the assembler that for any program instruction which refers to the data segment, it should use the logical segment called DATA. If, for example, the assembler reads the statement MOV AX,[BX] after it reads this ASSUME, it will know that the memory location referred to by [BX] is in the logical segment DATA.

(ii) ALIGN : The align directive is used to align the next segment at an address divisible by specified number. The general syntax for this directive is a shown below :
where n can be 2, 4, 8 or 16

(iii) CODE : The code directive is used to provide shortcut in definition of the code segment. General syntax for this directive is shown below : 
code [name]
The name is optional

(iv) DATA :  The data directive is used to provide shortcut in definition of the data segment.

(v) GROUPS : A program may contain several segments of the same type i.e code, data, or stack. The purpose of the GROUP is to collect them all under one hut, so that they reside within one segment, usually a data segment.
     Format : Name GROUP Seg -name,....., Seg-name.
(vi) LENGTH : It is an operator which tells the assembler to determine the number of elements in some named data item such as string or array.

(vii) MACRO and ENDM : The macros in the program can be defined by MACRO directive. ENDM directive is used along with the MACRO directive. ENDM defines the end of the macro.

(viii) NAME : The name directive is used at the start of a source program to give specific names, to each assembly module.

(ix) ORG : It is an assembler that uses a location counter to account for its relative position in a data or code segment.
     Format : ORG expression

(x) OFFSET : It is an operator which tells the assembler to determine the offset or displacement of a named data item ( variable) from the start of the segment which contains.

(xi) PAGE : The PAGE directive help to control the format of a listing of an assembled program. At the start of a program the PAGE directive specifies the maximum number of lines to list on a page and the maximum number of characters on a line.
     Format : PAGE [length], [width]

(xii) ENDP : ENDP directive is used along with PROC directive. ENDP defines the end of the procedure.

(xiii) TYPE : It is an operator which tells assembler to determine the type of specified variable. Assembler determines the type of specified variable in number of bytes. For byte type variable the assembler gives a value of 1. For word type variable the assembler gives a value of 2 and for double word type variable the assembler gives a value of 4.

The purpose of some instruction in 8086 microprocessor

The purpose of some instruction in 8086 microprocessor

    The concept of the instructions in the 8086 microprocessor is a very scoring topic. And its a good choice to set a question in the coming semester in December. The question about the instruction of 8086 microprocessor, lets the examiner to test the deep knowledge and the ability of the students. That's why you will find a question based on the instructions of 8086 microprocessor in almost every sample papers of B.Tech. So one can prepare these type of questions here with solutions.
The various instructions in 8086 microprocessor with example : 

(i) LOOP : This instruction is used to repeat a series of instructions some number of times. The number of times the instruction sequence is to be repeated is loaded into CX. Each time loop executes CX is decremented by 1.

  • If CX =/ 0 execution will jump to destination specified by label.
  • IF CX = 0 execution will go to the next instruction after loop.
(ii) RET : It POPs a word (16 bit) from the top of the stack into the IP(near return) and places it in IP and CS or 32 bit number(far return) and places it in IP and CS. The execution starts where from it left the main program. Its object code is C3. The stack has 0003H = IP. CS = 1000H, the new address = 10000H = 0003H.

(iii) AAM : Numerical data coming into a computer from a terminal through keyboard is usually in ASCH code. The numbers 0 to 9 are represented by ASCH codes 30 H to 39 H.
      Before multiplying two ASCH digits, the upper nibble bits of each need to be masked. This leaves unpacked CD in each byte. After the two unpacked BCD digits are multiplied, the AAM instruction is used to adjust the product of two upacked BCD digits in AX.
       It works only on register AL.
       It is used after multiplying the two unpacked BCD numbers.

(iv) MOVSB (Move string) :  This instruction copies a byte or a word from a location in the data segment to a location in the extra segment.
       The offset of the source byte/word in the DS must be SI register.
       The offset of the destination in ES must be in DI register.
       After byte or word is moved, SI and DI are automatically adjusted to point to the next source and next destination.

Explain the purpose of EU and BU in 8086 microprocessor

Explanation of the purpose of EU and BU in 8086

     Bus Interface Unit (BIU) : The  BIU interface 8086 to outside word. It provides full 16 bit bidirectional data bus and 20 bit address bus. The BIU is responsible for performing all external bus operations as given below : 

  1. It sends address of the memory or I/O.
  2. It fetches instruction from memory.
  3. It reads data from port/memory.
  4. It writes data into port/memory.
  5. It supports instruction queuing.
  6. It provides the address location facility.
      The BIU has a dedicated order. The main function of this order is to produce 20 bit physical address. The bus control logic of the BIU generates all bus control signals such as READ and WRITE for memory and I/O.

       Instruction Queue : To speed up program execution, the BIU fetches six instruction bytes ahead of time from memory. These prefetched instruction bytes are held for the execution unit in a group of registers called queue. With the help of queue it is possible to fetch next instruction while current instruction is in execution. There are number of instructions in 8086 microprocessor which need a quite large number of clock cycles for execution. During this execution time the BIU fetches the next instruction or instructions from memory into the instruction queue instead of remaining idle. Th BIU continues this process as long as the queue is not full. Due to this execution unit gets, the ready instructions in the queue and instruction fetch time is eliminated ( while decoding or executing an instruction EU does not require use of the buses).

       This system has the advantage over the 8085 microprocessor because, while EU is executing an instruction, the BIU is fetching and storing in the queue the next instructions.
       The BIU's instruction queue is based on first in first out (FIFO). So that the EU gets the instructions for execution in the order they are fetched. If the queue is full and EU does not request BIU for accessing memory, the BIU does not perform any bus cycle. On the other hand, if the queue is not full and even through the EU does not request BIU for accessing the memory the BIU can fill the queue on its own. If the EU interrupts the BIU, the BIU 1st completes the prefetching and then attains to the service of the EU.

       In case of JUMP and CALL instruction, instruction already fetched in queue are of no use. Hence, in these cases queue is dumped and newly formed by loading instructions from new address specified by JUMP and CALL instruction.

       Execution Unit (EU) :  The EU of 8086 tells the BIU from where to fetch instructions or data, decodes instruction and executes instructions. It contains :

  1. Control Circuitary
  2. Instruction Decoder
  3. Arithmetic Logic Unit (ALU)
  4. Flag register
  5. General purpose registers.
  6. Pointers and Index registers.
         The central circuitry in the EU directs the internal operation. A decoder in the EU translates the instructions fetched from memory into a series of actions which the EU performs. ALU is 6 bit. If can add, subtract, AND, OR, XOR, increment, decrements, complement and shift binary numbers
         In the beginning the CS :IP is loaded with the required address from which the execution is to be started. In the initial condition the queue will be empty and the microprocessor starts a fetch operation to bring one byte ( the first byte) of instruction code, if the CS : IP address is odd, and two bytes at a time, if the CS : IP address even. The first byte is a complete opcode in case of some instructions (one byte opcode instructions), the remaining part of opcode may lie in the second byte. But invariably the first byte of an instruction is an opcode. These opcodes along with data are fetched and arranged in the queue. When the first byte from the queue goes for decoding and interpretation, one byte in the queue becomes empty and subsequently the queue is up dated.
  • The microprocessor does not perform the next fetched operation till at least two bytes of the instruction queue are emptied. The instruction execution cycle is never broken for fetch operation. After decoding the first byte the decoding circuit decides whether the instruction is of single opcode byte or double opcode byte. If the single opcode bytes, the next bytes are treated as data bytes depending upon the decoded instruction length. Otherwise, the next byte in the queue is treated as the second byte of the instruction opcode.
  • The queue is updated after every byte is read from the queue but the fetch cycle is entreated by BIU only if at least two bytes of the queue are empty and the EU may be concurrently executing the fetched instructions. 
     The queue operation is shown in the figure below :
Queue operation 

Explain instructions format of 8086 microprocessor in detail.

Instructions format of 8086 microprocessor in detail.

      In 8086 all instruction will not be of same size. The instruction vary from 1 to 6 bytes in length. The length of instruction bytes is dependent  upon addressing mode used by programmer i.e. immediate, register relative, based indexed, relative based indexed and so on.

      Basically instruction bytes will contain information of :

  2. Addressing mode designations :
  • 2 byte Effective Address.
  • 1 or 2 byte displacement.
  • 1 or 2 byte immediate operand.
As shown in figure normally first byte is OPCODE byte, second byte normally specifies addressing mode.  Sometime it may also contain OPCODE part. After OPCODE and addressing mode bytes, we have following different cases :
  • No additional bytes 
  • A 2 byte EA ( for direct addressing mode.
  • A 1 or 2 byte immediate operand.
  • A 1 or 2 byte displacement followed by 1 or 2 byte immediate operand.
( REG - Register, MOD - Mode, R/M - Register or Memory DISP - Displacement, DATA - Immediate data. )

One - byte instruction - implied operand(s)
One - byte instruction - register mode
Register to Register

Register to/from memory with no displacement

Register to/from memory with displacement

Immediate operand to register

Immediate operand to memory with 16 bit displacement

       If a displacement or immediate operand is 2 bytes long, the low order byte always appears first, this is Intel standard.
Instruction format of 8086 microprocessor

       As shown in this figure the first six bits of multi byte instruction generally contains an opcode that identifies the basic instruction type i.e. ADD, XOR etc. The following bit, called the D field, generally specifies the direction of the operation.

        D = 1 means instruction source is specified in REG field.
        D = 0 meas instruction destination is specified in REG field.
The next following bit is W. This bit identifies between byte and word operation.
        W = 0 instruction operates on byte data
            = 1 instruction operates on word data
In this we have three single bit fields, S, V, Z.

      S bit : S bit is used in conjunction with W to indicate sign extension of immediate fields in arithmetic instructions.

     S = 0 No sign extension
        = 1 sign extended 8 bit immediate data to 16 bits if W = 1.

Therefore for 8 bit operations : S = W= 0
16 bit operation with a 16 bit immediate operand : S = 0, W = 1
16 bit operation with a sign extended 8 bit immediate operand : S =W = 1

     V bit :  Used by shift and rotate, to determine single and variable - bit shifts and rotate.

              V = 0 shift/rotate count is one
                 = 1 shift/rotate count is specified in CL register.

     Z bit : This bit is used as compare bit with zero flag in conditional repeat(REP) and loop instructions.

            Z = 0 Repeat/loop while zero flag is clear
               = 1 Repeat/loop while zero flag is set.

     MOD : The mode (MOD) field indicates whether one of the operands is in memory or whether both operands are register.

     REG : The register field identifies a register that is one of the instruction operands REG field depends upon W bit.

     R/M (Register or Momery)  : This field is of 3 bits. The meaning of R/M bits changes depending upon mode (MOD) field.

Junior Graphic Designer @The Jewish Museum New York

Department: Marketing & Communications
Reports to: Consulting Creative Designer
Date posted: September 20, 2017
FLSA Status: Non-Exempt
Schedule: Full-Time

The Junior Graphic Designer will create engaging materials and support the Museum’s overall graphic design project needs in support of the exhibitions, public programs, and institutional communications. Projects will include print and digital collateral, web content, e-communications and other digital media, environmental and exhibition design, and motion graphics related to institutional, exhibition, development, membership, education and program-related promotional needs. This position provides an exciting opportunity to work with the graphic design firm Topos Graphics.


  • Design attractive and effective promotional content including print collateral, website pages and calendar listings, e-communications, environmental and exhibition design, motion graphics and other general museum information; and social media content.
  • Work cross-departmentally on multiple publications.
  • Prepare design files for production.
  • Communicate with vendors and other service providers relating to design and fabrication.
  • Adhere to production schedules, budgets and deadlines.
  • Actively stay abreast of current design trends.


  • Bachelor’s degree in graphic design or similar.
  • Preferred minimum of one year of experience designing marketing collateral or advertisements, arts and cultural experience a plus.
  • Experience managing multiple projects within tight deadlines.
  • In-depth knowledge of design principles and techniques including web and digital design, web standards and related best practices. Motion and/or environmental design experience a plus.
  • Fluent in Adobe Creative Suite; InDesign, Illustrator, Photoshop. HTML, CSS, Keynote, PowerPoint, After Effects a plus.
  • Previous experience supporting brand requirements.
  • Excellent attention to detail, typesetting and typography.
  • Strong interpersonal skills including ability to take direction and build productive working relationships.
  • Interest in art and culture preferred.
For immediate consideration email resume, cover letter and samples of your design/website portfolio to:
Associate Director, Human Resources
The Jewish Museum
1109 Fifth Avenue
New York, NY 10128

The Jewish Museum is an Equal Opportunity Employer.

Describe 8086 Microprocessor architecture with its block diagram.

Describe 8086 Microprocessor architecture with its block diagram.

The 8086 is divided into two functional independent parts :

  1. BIU ( BUS Interface Unit )
  2. EU ( Execution Unit )
     Dividing the work between two unit speed up the processing.  The 8086 and the 8088 differs in their architecture of the BIU. The 8088 BIU provides 8-bit data path instead of 16-bit data path for 8086. EU is same for both the processor.

BIU :  Bus Interface Unit sends out address, fetches instruction from memory, reads data from port and memory and write data to ports and memory. In other words the BIU handles all transfer of data and address on the buses for EU. The following describe the function parts of the BIU :
  1. Instruction Queue
  2. Segment Registers
  3. Instruction Pointer
  4. Bus Interface and memory addressing Logic.
EU :  Execution unit of 8086 tells the BIU, where to fetch instruction and data from, decodes instruction and executes instruction. The following  sections describe functional parts of the execution unit. Goes for deciding and interpretation, one byte in the queue becomes empty and subsequently the queue is  updated. The microprocessor does not perform next fetch operation, till at least two bytes of the instruction queue are emptied.
Register Organisation of 8086 :

8086 Architecture

Explain flag manipulation instruction of 8086 in detail.

Explain flag manipulation instruction of 8086 in detail.

Flag Instructions (Flag Transfer) : These instructions are related to movement of flag register to/from a register and memory.

Flag Instructions (Flag transfer) :

  1. LAHF (Load AH register from flags)
  2. SAHF (Store AH register flags)
  3. PUSHF (Push flags onto stack)
  4. POPF (Pop flags off stack)
=> LAHF - Load AH register from flags : Copy lower byte of flag register to AH.

Mnemonic       LAHF       Flags       No flags are affected
Algorithm        AH = flag register's lower byte
Addr. Mode     Implied Addressing mode
Operation        AH <- Lower byte of flag register 
                        The lower byte of 8086 flag register is copied to the AH register.
=> SAHF - Store AH register in Flags : Copy contents of AH to lower byte of flag register

Mnemonic       SAHF          Flags      No flags are affected.
Algorithm         AH = flag register
Addr. Mode      Implied Addressing mode
Operation         AH -> Lower byte of flag register.
  • This instruction copies the contents of AH register to the lower byte of flag register.
  • It is included for 8085 compatibility.
  • The OF, DF, IF and TF are not affected.
=> PUSHF - Push flags onto stack : PUSH flag register on the stack

Mnemonic       PUSHF           Flags        No flags are changed.
Algorithm        SP = SP - 2
                       SS : [SP] (top of stack) = operand.
Addr. Mode     Register Addressing mode
Operation        SP -> SP -2        SS -> data from flag register
  • This instruction decrements the stack pointer by 2 and copies word in the flag register to the memory location pointed by stack pointer.
  • The stack segment register is not affected.
=> POPF - Pop flags off stack : 

Mnemonic     POPF                 Flags         All flags are affected.
Algorithm       SS = data to flag register    SP = SP + 2
Addr. Mode    Register Addressing mode
Operation       SS : [SP] -> Copy data to flag register        SP = SP +  2.
  1. This instruction copies a word from the two memory locations at the top of the stack to flag register and increment the stack pointer by 2.
  2. The stack segment register and word on the stack are not affected.

Discuss in detail 8085 interrupts.

This is another favourite topic for the examiner to set a question questions. So students need prepare it strongly. In the coming B.Tech 5th semester examination, you will definitely find one question on the this topic i.e. 8085 microprocessor interrupts. As MDU university used to held semester examination in December. The concept of 8085 microprocessor interrupts is very easy to prepare for the examination and its a very scoring topic in the subject of Microprocessor and interfacing. 

Discuss in detail 8085 interrupts.

8085 Interrupts :  The interrupt driven I/O is one of the data transfer techniques used in the microprocessor systems. By using this techniques, the external device or a peripheral can inform the microprocessor that it is ready for communication.

    In 8085 microprocessor there are two types of interrupts : Hardware and software interrupts.
Hardware Interrupts :  8085 microprocessor provides five hardware interrupt viz TRAP, RST 7.5, RST  6.5, RST 5.5, and INTR.  The interrupt structure is a five level structure.
  1. TRAP :  It is non-maskable edge and level triggered interrupt, request input line.  It is used for emergency purpose like power failure, parity error checker, smoke detector etc. The microprocessor does not execute any interrupt acknowledge cycle to read interrupt information from the interrupting device. The interrupt information is provided by control section of microprocessor internally. But microprocessor executes ideal machine cycle to acknowledge this interrupt. To generate starting address of TRAP interrupt service routine.  The TRAP signal must make low to high transition and remain high until acknowledged that means this interrupt is triggered only at the rising edge of the signal. This avoids false triggering due to noise or glitches. It is not affected by any instruction. It has the highest priority among all interrupt. It is always enabled. This interrupt transfers microprocessors control to location 0024 H. User cannot rest TRAP flip-flops that means we cannot cancel this interrupt.
  2. RST 7.5 :  It is maskable edge triggered interrupt request input line. The microprocessor does not execute any interrupt acknowledge cycle to read interrupt information from the interrupting device. The interrupt is provided by control selection of microprocessor internally. Instead of interrupt acknowledge cycle, the microprocessor executes ideal machine cycle (6T) to acknowledge this interrupt. During this cycle it executes RST 7.5.  Instruction to generate starting address of interrupt service routine. This interrupt is triggered at the rising edge of the signal. Its priority among all maskable interrupt. This interrupt to location 003ch. User can reset RST 7.5 flip-flop that means we can cancel this interrupt by SIM instruction.
  3. RST 6.5 and RST 5.5 : These are level triggered maskable interrupt request input lines. The microprocessor does not execute any interrupt acknowledge cycle to read interrupt information from the interrupting device. The microprocessor executes idle machine cycle (6T) to acknowledge these interrupts. During this cycle it executes RST 6.5 and RST 5.5 instructions to generate address of ISR 6.5 and ISR 5.5 respectively. They can be disabled by executing SIM or EI instruction. RST 6.5 transfers microprocessor's control to location 0034 H while RST 5.5 transfers microprocessor's control to location 002 CH.

The Table shows address of ISR’s
ISR address
RST 7.5
RST 6.5
RST 5.5
  • INTR :  It is level triggered, maskable interrupt request input line. The microprocessor executes interrupt acknowledge cycle to read interrupt information from interrupting device. The microprocessor executes one interrupt acknowledge cycle (6T) and three interrupt acknowledge cycles (6T + 3T +3T) for RSTN and CALL instructions respectively.
            The starting address of ISR depends upon interrupt information. This interrupt is not affected by SIM instruction. It is enabled by executing EI instruction while disabled by DI instruction.

Software interrupts :
  1. In case of software interrupts the cause of the interrupt the cause of the interrupt is the execution of the instruction.
  2. The microprocessor 8085 has eight instructions. These eight instructions are RST 0 to RST 7. Such interrupts are called as software interrupts.
  3. They allow the microprocessor to transfer program control from the main program to the subroutine program (i.e predefined service routine addresses).
  4. After completing the subroutine program, the program control returns back to the main program.

Pin diagram of 8085 and description of various signals

    This is one of the favourite topic for the examiners.  As you can see almost every year comes a question based on the pin diagram of microprocessor 8085 and its various pins description. If you see previous years sample papers of Microprocessor and interfacing, you will be able to find it how important this topic/concept is. So i do recommend to prepare this question for the coming December semester  2018. Students can prepare this topic through the notes they may have made during the semester if any case one can find all the useful and important concepts, topics, notes here on my website. For more updates on the topics, notes or latest Sample papers of B.Tech keep on watching my website. So here's your topic below happy reading/self studying.

Pin diagram of 8050 and description of various signals

     It is an 8-bit general purpose microprocessor capable of addressing 64kb of memory.  The device has 40 pins and works on +5v single power supply.  It is a TTLIC. Lets see the pin diagram of 8085 with direction of signals.
Pin diagram of 8085 Microprocessor

The various signals can be classified into six groups :-
  1. Address bus
  2. Data bus
  3. Control and status signals
  4. Power supply and frequency
  5. Externally initiated signals
  6. Serial I/O ports.

  • A8 - A15 : Address bus :-  These are unidirectional O/P tristate signals, used as higher order 8 bit of 16 bit address.  These signals are unidirectional meaning that the address is given by 8085 to select a memory or an I/O device. Address line A8 - A15 are used to send higher order 8 bit address from microprocessor to memory.  These lines are tristated by 8085 in response of following signals : (1) Reset (2) Hold (3) Halt.
  • AD0 - AD7 : Multiplexed address/data bus : These are bidirectional i.e. input/output. Tristate signals having two set of signals they are address and data. The lower 8 bits of 16 bit address (i.e. A0 - A7) is multiplexed or time shared with data bus ( D0 - D7). From same 8 bit line two types of signals are transmitted.
     All the operations of the microprocessor are performed sequentially with reference to the clock.  Microprocessor perform an operation in a specific period, that is known as operation cycles.
    In an operations cycle during earlier part it is used as lower address and in later part it is used as data bus. But for peripheral devices we want separate address and data signals so these signals are demultiplexed by using latch and ALE signal.  These lines are tristated by 8085 for condition same as A8 - A15.

  Various signals are as follows :
  1. Power supply signals
  2. clock signals
  3. DMA request signals
  4. reset signals
  5. interrupt signals
  6. status and control signals
  7. serial I/O signals
(1). Power Supply signals :

(i) Vcc and Vss
  • Vcc is to be connected to +5v power supply.
  • Vss - Ground reference.

(2). Clock Signals :-

(i) X1, X2 :
  • These are clock input signals, connected to crystal. LC or RC network.  The crystal, LC or RC is connected between these two pins.
  • The X1 and X2 pins drive the internal clock generator circuit.  Hence, externally only one crystal is enough.
  • The frequency is divided by 2 and used as operating frequency.  Generally the 6.014 MHz crystal is connected to X1 and X2, this is divided by 2.  So the operating frequency of 8085 is 3.07 MHz.

(ii) CLK OUT :
  • This is an output signal, used as a system clock.
  • The internal operating frequency is available on CLK OUT pin.
  • This pin can be used by the peripherals as a system clock input for their operation. Hence, there will be synchronisation between the different peripherals and the microprocessor.
(3) Reset Signals : 

(i) RESETIN : 
  • This is an active low, input reset signal.  When RESETIN = 0, it clears program counter i.e 0000 and makes address, data and control lines tristated.  After reset the status of internal register and flags are unpredictable.  The instruction register is reset. Halt flip-flop is reset. The program counter is reset.  All maskable interrupts are disabled. Also, other peripherals along with 8085 are reset.
  • The CPU is held in the reset condition as long as RESETIN is applied.
  • After reset the microprocessor starts executing instructions from 0000 H on wards.
(ii) Reset Out :
  • This is an active high, output signal used to indicate that the microprocessor is reset.
  • This signal is used as system reset, to reset other devices connected in system.

(4) Interrupt Signals :

(i) TRAP : 
  • This is an active high level and edge triggered, non maskable, vectored highest priority interrupt.
  • When TRAP line is active microprocessor performs internal restart automatically at vector address 0024 H.
(ii) Reset interrupts (RST 7.5, RST 6.5, RST 5.5) :
  • These are active high level, triggered, vectored, maskable interrupt.  They cause an internal restart to be automatically inserted.
  • The priorities of these are RST 7.5, RST 6.5 or RST 5.5.
  • When RST 7.5, RST 6.5 or RST 5.5 is active microprocessor performs internal restart automatically at vector addresses 003C H, 0034 H, 002C H respectively.
(iii) INTR :
  • INTR is an active high, level triggered general purpose, non-vectored interrupt.
  • It has the lowest priority.
  • Whenever a device requires a service it has to request service on this pin by making it's logic "I".
  • The interrupting device has to state where the interrupt service is placed in the memory.
(iv) INTA :
  • It is an output signal.
  • INTA is used to indicate that the microprocessor has received an INTR interrupt.
(v) Status and Control Signals :

(i) Address latch enable (ALE) :
  • This is an output signal, used to give information of AD0 - AD7 contents.
  • It is a positive going pulse generated during the first clock cycle of a machine cycle.
  • When pulse is high it indicates that the contents of AD0 - AD7 (i.e. demultiplex) to A0 - A7 are address.  When it is low it indicates that the contents are data.
  • The ALE signal is used to separate AD0 - AD7(i.e demultiplex) to A0 - A7 and D0 - D7. To do this separation an external latch is connected to AD0 - AD7 lines and this latch is controlled by ALE signal.
(ii) Input output/memory (IO/M) :
  • This is an output status signal, used to give information of operation to be performed with memory or I/O device.
  • If IO/M = 0, the microprocessor is performing a memory related operation.
  • If IO/M = 1, the microprocessor is performing an I/O device related operation.
(iii) Read (RD) : 
  • This is an active low signal.
  • It is an output control signal that is used to read data from the selected memory location or an I/O location via data bus.
  • A low on this pin indicated that an operation performed is a read operation.
(iv) Write (WR) :
  • It is an output control signal used to write data to selected memory location or an I/O location via data bus.
  • This is an active low signal.
  • A low on this pin indicated that an operation performed is write operation.

Data Engineer @National Geospatial-Intelligence Agency, St. Louis, USA Full Time

Title, PP, Series, Band
Data Engineer

Pay Band, Salary Range - Ext
Band 03   $60,613 - $123,234
Band 04   $86,391 - $145,629
Band 05   $120,083 - $161,900

Permanent Change in Station
PERMANENT CHANGE IN STATION: PCS expenses are authorized.

Additional Information
Data Engineers develop, construct, test, and maintain architectures such as databases and large-scale data processing systems. They clean, prepare, and optimize data for consumption through the design and construction of massive reservoirs for big data. They solve problems associated with database access and integration and unstructured data sets to provide clean, usable data for customers and IT counterparts. These engineers serve as integrators between data architects, data scientists, and other data consumers. They apply knowledge of scripting tools, programming languages, standards, and software packages to build the data pipelines that enable faster, better, data-informed decision-making within the Agency.
Duties include, but are not limited to, the following:
Band 3:
* Utilize a variety of languages and tools (e.g., scripting languages) to build data pipelines to pull together information from different source systems
* Collaborate with data architects, modelers, and IT team members on project goals; ensure systems meet Agency requirements and industry practices
* Design, construct, install, test, and maintain highly scalable data management systems
* Develop data set processes for data discovery, modeling, mining, and production
Band 4:
* Utilize a variety of languages and tools (e.g., scripting languages) and create custom software components and analytics applications to build data pipelines to pull together information from different source systems
* Collaborate with data architects, modelers, and IT team members on project goals; research emerging systems, opportunities for data acquisition, and new uses for existing data
* Integrate data management technologies and software engineering tools into data management systems
* Design, build, and test algorithms, prototypes, predictive models, and proof of concepts
Band 5:
* Oversee the development of data pipelines used to pull together information from different source systems
* Maintain robust internal network and facilitate collaboration with data architects, modelers, and IT team members on project goals
* Identify and recommend ways to improve data reliability, efficiency, and quality in existing data management systems; advise regarding feasibility of integrating emerging data management systems
* Serve as advisor regarding data management technologies, software engineering tools, and facilitate the innovation of systems and tools
Competencies (across all Pay Bands):
* Advising -- provides guidance and expertise to internal and external customers on policies, procedures, technologies, issues, and other organizational requirements.
* Customer Requirements Generation/Management -- demonstrates knowledge of how to build, prioritize, levy, track, review, and validate customer requirements and ensure they are documented and measurable.  Includes actions to resolve conflicts between customers and the acquisition community.

* Data Information/Management -- formats, catalogs, and/or filters data and information to facilitate data access, integration, and interpretation.
* Data Modeling -- develops, modifies, and evaluates formal descriptions of data and data structures as defined by a standard (e.g., respective definitions, data semantics, data syntax, associated metadata).
* Data Preparation -- accesses, converts, formats, cleans, merges, and normalizes data in advance of scientific and quantitative analysis.
* Data Standards -- knowledge of agency, industry, and other relevant data standards.
* Database Development -- applies database design principles to develop database and file structures.
* Scripting and Coding -- develops scripts, queries, or software code to accomplish a specific requirement or task.
* Technology Evaluation -- evaluates software, tools, and technologies for future use, and analyzes the potential impacts of new technologies. Identifies technology trends and opportunities.
* Testing & Evaluation -- develops test and evaluation plans, designs and conducts appropriate systems/software tests/evaluations, and documents and distributes results.
Qualifications Desirable
A. Bachelor's degree in Computer Science, Applied Mathematics, Management Information Systems, Engineering, Physical Sciences, or any other technology related field. -OR- B. Combination of Education and Experience: A combination of education and experience that demonstrates the ability to successfully perform the tasks associated with this work. As a rule, every 30 semester (45 quarter) hours of college work is equivalent to one year of experience. Candidates should show that their combination of education and experience totals to 4 years. -OR- C. Three years of experience or training in data engineering and related technologies.
DCIPS Statement
This position is a DCIPS position in the Excepted Service under 10 U.S.C. 1601.  DoD Components with DCIPS positions apply Veterans' Preference to preference eligible candidates as defined by Section 2108 of Title 5 USC, in accordance with the procedures provided in DoD Instruction 1400.25, Volume 2005, DCIPS Employment and Placement. If you are an external applicant claiming veterans' preference, as defined by Section 2108 of Title 5 U.S.C., you must self-identify your eligibility in our ERecruit application.
For more information on the array of benefits programs, please visit https://www.nga.mil/Careers/Benefits/Pages/default.aspx.
How To Apply
NGA is an equal opportunity employer. All candidates will be considered without regard to race, color, religion, sex, national origin, age, marital status, disability, or sexual orientation. NGA provides reasonable accommodations to applicants with disabilities.
To apply for this position, application instructions can be found by visiting https://www.nga.mil/Careers/Ap... and reading the FAQs. All announcements close at 7:59PM EST on the closing date listed. Be sure to complete and submit your application by that time in order to be considered. An incomplete application will be ineligible for consideration. ONLY ELECTRONIC SUBMISSIONS WILL BE ACCEPTED.
Special Requirements
As a condition of employment at NGA, persons being considered for employment must meet NGA fitness for employment standards.
* US Citizenship
* Security Clearance (Top Secret/Sensitive Comparted Information)
* Polygraph
* Direct Deposit
* Two-year trial period
* Position is subject to Drug Testing



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