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Write a program to calculate the sum of the series of even numbers.


Write a program to calculate the sum of the series of even numbers.

Program statement :- Write a program in the ALP of 8085 to calculate the sum of series of even numbers. Assume that the length of the series is stored at memory location D000 H and the series itself begins at memory D001 H. Store the result at memory location E000 H. Draw flowchart.

   Explanation :-
  1. Initialize the sum to zero. Load the count of numbers in register C. Iniialize pointer to start of series.
  2. To check whether the number is even we will AND the number with 01 H. If the result of ANDing is zero it indicates that the number is even. We will add this even number to the initialised sum.
  3. Decrement counter Increment source pointer to next location. Continue the process till sum of all even numbers is found. Store the sum at memory location E000 H.
Program :
Lable
Instruction
Comment

LDA D000H
MOV C,A
MVI B, 00 H
LXI H, D001 H

Initialize counter
sum = 0
Initialize pointer
Back :
MOV A,M
ANI 01 H
JNZ SKIP
MOV A,B
ADD M
MOV B,A
Get the number
Mask Bit 1 to Bit 7
Don’t add if number is Odd
Get sum
SUM = Sum + data
Store result in B register
SKIP:
INX H
DCR C
JNZ BACK
STA E000H
HLT
Increment pointer
Decrement counter
If counter =/ 0 repeat
Store sum (Result)
Terminate program execution


Explain Pin diagram of 8085 microprocessor.


    This is one of the favourite topic for the examiners.  As you can see almost every year comes a question based on the pin diagram of microprocessor 8085 and its various pins description. If you see previous years sample papers of Microprocessor and interfacing, you will be able to find it how important this topic/concept is. So i do recommend to prepare this question for the coming December semester  2018. Students can prepare this topic through the notes they may have made during the semester if any case one can find all the useful and important concepts, topics, notes here on my website. For more updates on the topics, notes or latest Sample papers of B.Tech keep on watching my website. So here's your topic below happy reading/self studying.

Pin diagram of 8050 and description of various signals

     It is an 8-bit general purpose microprocessor capable of addressing 64kb of memory.  The device has 40 pins and works on +5v single power supply.  It is a TTLIC. Lets see the pin diagram of 8085 with direction of signals.
Pin diagram of 8085 Microprocessor

The various signals can be classified into six groups :-
  1. Address bus
  2. Data bus
  3. Control and status signals
  4. Power supply and frequency
  5. Externally initiated signals
  6. Serial I/O ports.

  • A8 - A15 : Address bus :-  These are unidirectional O/P tristate signals, used as higher order 8 bit of 16 bit address.  These signals are unidirectional meaning that the address is given by 8085 to select a memory or an I/O device. Address line A8 - A15 are used to send higher order 8 bit address from microprocessor to memory.  These lines are tristated by 8085 in response of following signals : (1) Reset (2) Hold (3) Halt.
  • AD0 - AD7 : Multiplexed address/data bus : These are bidirectional i.e. input/output. Tristate signals having two set of signals they are address and data. The lower 8 bits of 16 bit address (i.e. A0 - A7) is multiplexed or time shared with data bus ( D0 - D7). From same 8 bit line two types of signals are transmitted.
     All the operations of the microprocessor are performed sequentially with reference to the clock.  Microprocessor perform an operation in a specific period, that is known as operation cycles.
    In an operations cycle during earlier part it is used as lower address and in later part it is used as data bus. But for peripheral devices we want separate address and data signals so these signals are demultiplexed by using latch and ALE signal.  These lines are tristated by 8085 for condition same as A8 - A15.

  Various signals are as follows :
  1. Power supply signals
  2. clock signals
  3. DMA request signals
  4. reset signals
  5. interrupt signals
  6. status and control signals
  7. serial I/O signals
(1). Power Supply signals :

(i) Vcc and Vss
  • Vcc is to be connected to +5v power supply.
  • Vss - Ground reference.

(2). Clock Signals :-

(i) X1, X2 :
  • These are clock input signals, connected to crystal. LC or RC network.  The crystal, LC or RC is connected between these two pins.
  • The X1 and X2 pins drive the internal clock generator circuit.  Hence, externally only one crystal is enough.
  • The frequency is divided by 2 and used as operating frequency.  Generally the 6.014 MHz crystal is connected to X1 and X2, this is divided by 2.  So the operating frequency of 8085 is 3.07 MHz.

(ii) CLK OUT :
  • This is an output signal, used as a system clock.
  • The internal operating frequency is available on CLK OUT pin.
  • This pin can be used by the peripherals as a system clock input for their operation. Hence, there will be synchronisation between the different peripherals and the microprocessor.
(3) Reset Signals : 

(i) RESETIN : 
  • This is an active low, input reset signal.  When RESETIN = 0, it clears program counter i.e 0000 and makes address, data and control lines tristated.  After reset the status of internal register and flags are unpredictable.  The instruction register is reset. Halt flip-flop is reset. The program counter is reset.  All maskable interrupts are disabled. Also, other peripherals along with 8085 are reset.
  • The CPU is held in the reset condition as long as RESETIN is applied.
  • After reset the microprocessor starts executing instructions from 0000 H on wards.
(ii) Reset Out :
  • This is an active high, output signal used to indicate that the microprocessor is reset.
  • This signal is used as system reset, to reset other devices connected in system.

(4) Interrupt Signals :

(i) TRAP : 
  • This is an active high level and edge triggered, non maskable, vectored highest priority interrupt.
  • When TRAP line is active microprocessor performs internal restart automatically at vector address 0024 H.
(ii) Reset interrupts (RST 7.5, RST 6.5, RST 5.5) :
  • These are active high level, triggered, vectored, maskable interrupt.  They cause an internal restart to be automatically inserted.
  • The priorities of these are RST 7.5, RST 6.5 or RST 5.5.
  • When RST 7.5, RST 6.5 or RST 5.5 is active microprocessor performs internal restart automatically at vector addresses 003C H, 0034 H, 002C H respectively.
(iii) INTR :
  • INTR is an active high, level triggered general purpose, non-vectored interrupt.
  • It has the lowest priority.
  • Whenever a device requires a service it has to request service on this pin by making it's logic "I".
  • The interrupting device has to state where the interrupt service is placed in the memory.
(iv) INTA :
  • It is an output signal.
  • INTA is used to indicate that the microprocessor has received an INTR interrupt.
(5) Status and Control Signals :

(i) Address latch enable (ALE) :
  • This is an output signal, used to give information of AD0 - AD7 contents.
  • It is a positive going pulse generated during the first clock cycle of a machine cycle.
  • When pulse is high it indicates that the contents of AD0 - AD7 (i.e. demultiplex) to A0 - A7 are address.  When it is low it indicates that the contents are data.
  • The ALE signal is used to separate AD0 - AD7(i.e demultiplex) to A0 - A7 and D0 - D7. To do this separation an external latch is connected to AD0 - AD7 lines and this latch is controlled by ALE signal.
(ii) Input output/memory (IO/M) :
  • This is an output status signal, used to give information of operation to be performed with memory or I/O device.
  • If IO/M = 0, the microprocessor is performing a memory related operation.
  • If IO/M = 1, the microprocessor is performing an I/O device related operation.
(iii) Read (RD) : 
  • This is an active low signal.
  • It is an output control signal that is used to read data from the selected memory location or an I/O location via data bus.
  • A low on this pin indicated that an operation performed is a read operation.
(iv) Write (WR) :
  • It is an output control signal used to write data to selected memory location or an I/O location via data bus.
  • This is an active low signal.
  • A low on this pin indicated that an operation performed is write operation.
(v) Ready : It is used by the microprocessor to sense whether a peripheral is ready or not for data transfer. If not, the processor waits. It is thus used to synchronize slower peripherals to the microprocessor. If peripherals are fast enough it is tied to Vcc. If it is left open, 8085 enters in the wait state.

What do you mean by Data Structure ? Describe different types of Data Structure ?



Q.1. What do you mean by Data Structure ? Describe different types of Data Structure ?
Ans. Data Structure : A data structure is a class of data that can be characterised by its organization and the operations that are defined on it. Hence
Data Structures = Organised data + Allowed operations

In other words, the organised collection of data is called data structure.
Let us now formally define a Data Structure.
     A data structure is a set of values along with the set of operations permitted on them. It is also required to specify the semantics of the operations permitted on the data values, and this is done by using a set of axioms, which describes how these operations work, and therefore a data structure is made of
  • A set of data values
  • A set of functions specifying the operations permitted on the data values.
  • A set of axioms describing how these operations work.
Classification of Data Structure : There are various ways to classify data structure.
  • Primitive and Non-Primitive data structure :  The data structure that are atomic (indivisible) are called primitive. Example are integer, real, boolean and characters. 
            The data structures that are not atomic are called non primitive or composite. Example are records, array and string.
  • Linear and Non-Linear data structure : In a linear data structure, the data items are arranged in a linear sequence. Example is array. 
      In a non-linear data structures, the data items are not in sequence. Example is tree.
  • Homogeneous and Non-Homogeneous data structure : In homogeneous structures, all the elements are of same type. Example is arrays.
      In non-homogeneous structures, the elements may or may not be of the same type. Example is Records.
  • Static and dynamic data structures : Static structures are ones whose size and structures, associated memory location are fixed at compile time.
      Dynamic structures are ones which expand or shrink as required during the program execution and there associate memory location change.
 

Write Reverse algorithm for binary search.



Write Reverse algorithm for binary search.

    The Reverse method reverses the order of the elements in an array.
    BinarySearch(): performs a binary search on the list of elements.
    Sort(): Sorts the items
    Reverses items
{

int mid;
int first = 0;
int last = list.length(-) - 1;
while ( first <= last )
{
mid = (first + last)/2;
if ( list[mid] == target )
return mid;
if ( list[mid]>target )
last = mid - 1;
else
first = mid + 1;
}
return - 1;
}
Sorting :{
Intmain()
Intarray[] = {};
Int elements = sizeof(array);
Std::sort(array,array + elements);
For(int=0, i<<elements, i++)
Std::cout<<array[i]<<' ';
}
Reverse the array:
{
int n,c,t,end,array[];
for(c=0, c<n/2, c++)
{
t = array[c];
array[c] = array[end];
array[end] = t;
}

Short notes on Priority Queues, Dynamic Allocation, Tree Reversal and File organization.



Data Structures short notes on some of the important topics

(a) Priority Queues : Priority queue is an ordered list of homogeneous elements. In a normal queue, service is provided on the basis of First-in-first-out. In priority queue, service is not provided on the basis of "first-come-first-served" basis but rather than each element has a priority based on the urgency of need.

  • An element with higher priority is processed before other elements with lower priority.
  • Elements with the same priority are processed on "first-come-first served" basis.
An example of priority queue is found in long term scheduling of jobs processed in a computer. In practice, short processes are given a priority over long processed as it improves the average response of the system.

     Implementation of Priority Queues : Priority queue can be implemented using a circular array. As the service must be provided to an element having highest priority, there could be a choice between :
  1. List is always maintained sorted on priority of elements with the highest priority element at the front. Here, deletion is trivial but insertion is complicated as the element must be inserted at the correct place depending on its priority.
  2. List is maintained in the "FIFO" form but the service is provided by selecting the element with highest priority. Deletion is difficult as the entire queue must be traversed to locate the element with highest priority. Here, insertion is trivial (at rear end).
Applications of Priority Queues : Priority Queues are used in following areas :
  1. Operating System : Priority queue is used for job scheduling and interrupt handling in operating system.
  2. Graph Searching : It is used for shortest path graph searching.
  3. Event-driven simulation : It is used for customers in a line.
  4. Data Compression : It is used for Huffman codes.
  5. Numerical Computation : It is used for reducing round off error.
  6. Computational number theory : It is used to find the sum of powers.
  7. Artificial Intelligence : It is used of A* search.
(b) Dynamic Allocation : The process of allocating memory at the time of execution is called dynamic memory allocation. The allocation and release of this memory space can be done with the help of some built-in-functions whose prototypes are found in alloch.h and stdlib.h header files. These functions tame memory from a memory area called heap and release this memory whenever not required, so that it can be used again for some other purpose.

      Pointers play an important role in dynamic memory allocation for some other purpose. The dynamically allocated memory only through pointers.

malloc()
Declaration : void * malloc (size_t size)
calloc()
Declaration : void * calloc (size_t n, size_t size)
realloc()
Declaration : void * realloc (void*ptr, size_t size)
Free()
Declaration : void free(void *P)
    Example for allocating dynamic memory for storing 100 numbers using malloc() :

   int *P;
                P = (int*)malloc (100*sizeof(int));

    On successful execution of the above statement, a memory space of the size 100* size of an integer in byte is reversed and the address of the first byte of the memory allocated is assigned to the pointer P.

      Example for allocating dynamic memory for storing 100 integer numbers using calloc().

  int *P;
  P = (int*) calloc (100, sizeof(int));

The above statement allocates contiguous space for 100 blocks, each of size 'sizeof(int)'. All bytes are initialized to zero and pointer to the first byte of allocated memory is assigned to pointer P.

(c) Tree Reversal : Most of the tree operation require traversing tree in particular order. Traversing a tree is a process of visiting every node of the tree and exactly once. Since, a binary tree is defined in a recursive manner, tree traversal too could be defined recursively. For example, to traverse a tree, one may visit the root first, then the left subtree and finally traverse the right subtree. If we impose the restriction than left subtree is visited before the right subtree then free different combination of visiting the root, traversing left subtree, traversing right sub-tree is possible.
  1. Visit the root, traverse, left sub-tree, traverse right sub-tree.
  2. Traverse left subtree, visit the root, traverse right subtree.
  3. Traverse left subtree, traverse right subtree, visit the root.
   These three techniques of traversal are known as Preorder, inorder and postorder traversal of a binary tree.

   Preorder Traversal (Recursive) : The functioning of preorder traversal of a non-empty binary tree is as follows :
  1. Firstly, visit the root mode.
  2. Next, traverse the left subtree in pre-order.
  3. At last, traverse the right-subtree in preorder.
   Inorder Traversal (Recursive) : The functioning of inorder traversal of non-empty binary tree is as follows :

  1. Firstly, traverse the left sub-tree in-order.
  2. Next, visit the root node.
  3. At last, traverse the right subtree in in-order.
    Postorder Traversal (Recursive) : The functioning of postorder traversal of nonempty binary tree is as follow :

  1. Firstly, traverse the left subtree in postorder.
  2. Next, traverse the right subtree in postorder.
  3. At last, visit the root node.

(d). File organization : A file is a collection of records where each record consists of one or more fields. File organization can be defined as the method of storing data records in a file. The primary objective of file organization is to provide means for record retrieval and update. The factors involved in selecting a particular file organization for uses are :
  1. Economy of storage 
  2. Ease of retrieval
  3. Convenience of updates
  4. Realiability
  5. Security
  6. Integrity
  7. Volume of transcation
Commonly, used file organization are :
  1. Sequential files
  2. relative files
  3. Direct files
  4. Indexed Sequential files
  5. Index files
    In a sequential file, data records are stored in specific sequence. Records are physically ordered on the value of one the fields called the ordering fields. Records could also be stored in the order of arrival.

     In a relative file, each record is stored at a fixed place in a file. Each record is associated with a integer key value, which is mapped to fixed slot in a file.

     Direct file is similar to relative file. Direct file popularly known as a hashed file. Here the key value need not be an integer.

     In an indexed sequential file an index is added to a sequential file to provide random access. An overflow are should be maintained to allow insertions.

    In an index file, data records need not be sequenced. An index is maintained to improve access.

Data Structure using C Dec 2012 sample paper CSE-201-F



Data Structure using C Dec 2012 sample paper CSE-201-F

(a) Priority Queues
(b) Dynamic Allocation
(C) Tree Reversal
(d) File organization

Q.2. 
(a). Write Reverse algorithm for binary search.
(b). What do you mean by Data Structures ? Describe different types of Data Structures.

Q.3. What is "stack". How a stack can be represented in memory ? Also describe various application of stack.

Q.4. Write an algorithm to insert and delete an element from double linked list.

Q.5. Give linked implementation of queues.

Q.6.
(a). Explain threaded binary trees in detail.
(b). Explain the concept of B trees in detail.

Q.7. What is Graph ? Give Set, Linked and matrix representation of graphs.

Q.8. How file can be managed in C ? Explain with example.

Q.9. Write short notes on :
(a) AVL Trees
(b) Skip Lists.

Explain direct memory access.


Explain direct memory access.

      Direct memory access (DMA) :- It is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit(CPU).
     Without DMA, when the CPU is using programmed input/output, it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU initiates the transfer, does other operations while the transfer is in progress, and receives an interrupt from the DMA controller when the operations is done. This feature is useful any time the CPU cannot keep up with the rate of data transfer, or where the CPU needs to perform useful work while waiting for a relatively slow I/O data transfer. Many hardware systems use DMA, including disk drive controllers, graphics cards, network cards and sound cards. DMA is also used for intra-chip data transfer in multi-core processors. Computers  that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without DMA channel. Similarly, a processing element inside a multi core processor can transfer data to and from its local memory without occupying its processor time, allowing computation and data transfer to proceed in parallel.


What is programmable interval timer ?


What is programmable interval timer ?

      There are two types of programmable interval timer are generally used. Intel 8253 is a programmable Interval Timer/Counter which can generate accurate time delays and wave forms ranging from 0 HZ to 2 MHz using software control. 8254 is its upgraded version which can operate with higher clock frequency range (DC - 8 MHz) and it is pin to pin compatible with 8253.

What are NOP and HLT instructions ?



What are NOP and HLT instructions ?

NOP Instruction :

Mnemonic      NOP           Flags : It does not affect any flag.
                    NOP : No operation
Algorithm      Do nothing
Addr. mode    Implied addressing mode
Operation      The execution of this instruction causes the CPU to do nothing.

  1. This instruction causes the CPU to do nothing. This instruction uses three clock cycles and increments the instruction pointer to point to the next instruction.
  2. It can be used to increase the delay of a delay loop.
Example : 
MOV AL, 00011011b
NOT AL ; AL = 11100100b
RET
Flags : All unchanged.

HLT (Halt until interrupt or reset) Instruction :

Mnemonic      Halt processing           Flags : No flags are affected.

Operation :
  1. The HLT instruction will cause the 8086 to stop fetching and executing instructions. The 8086 enters into a half state. To come out of the halt state, there are 3 ways : (a) Interrupt signal on INTR pin, (b) Interrupt signal on NMI pin, (c) Reset signal on reset pin.
  2. It may be used as an alternative to an endless software loop in situations where a program must wait for an interrupt.

Write a program to find 1's complement of the number.



Write a program to find 1's complement of the number.

       Statement : Find the 1's complement of the number stored at memory location 2200H and store the complemented number at memory location 2300H.
Sample problem:
(2200H) = 55H
Result = (2300H) = AAH

Program :

LDA 2200H -> Get the number
CMA -> Complement number
STA 2300H -> Store the result
HLT -> Terminate program execution.


 

Microprocessing and Interfacing Dec 2016 sample paper Code-EE-309-F



Microprocessing and Interfacing
Dec 2016
Paper Code-EE-309-F

Q.1

Q.2

Q.3
(b) What is the functioning of timing and control unit in 8085 microprocessor? Discuss all its signals in details.

Q.4
(b) Discuss Pipelining .

Q.5
(b) How physical address is computed in 8086 microprocessor ?

Q.6. Write a simple assembly program to subtract two memory location, where each memory location is one byte wide.

Q.7
(a) Write short notes on directives and operators.
(b) Write a 8086 assembly language program to find largest number in data array.

Q.8. Explain 8259 interrupt controller with the help of block diagram.

Q.9. Explain the following :
(a) 8253/8254 programmable interval timer.
(b) Instruction register and priority resolver.

Explain 8259 interrupt controller with the help of block diagram.


Explain 8259 interrupt controller with the help of block diagram.

   It contains following blocks :
Functional block diagram of 8259 interrupt controller


  • Data bus buffer : It is used to transfer data between microprocessor and internal bus.
  • Control logic : It generates an INT signal. In response to an INTA signal, it releases three byte CALL address or one byte vector number. It controls read/write control logic, cascade buffer/comparator, in service register, priority resolver and IRR.
  • Cascade buffer and comparator : In master mode, it functions as a cascaded buffer. The cascaded buffers outputs slave identification number on cascade lines. In slave mode, it functions as a comparator. The comparator reads slave identification number from cascade lines and compares this number with its internal identification number. In buffered mode it generates an EN signal.
  • Read/write logic : It sets the direction of data bus buffer. It controls all internal read/write operations. It contain initialisation and operation command register.
  • IRR(Interrupt Request Register) : It is used to store all pending interrupt requests. Each bit of this register is set at the rising edge or at the high level of the corresponding interrupt request line. The microprocessor can read contents of this register by issuing appropriate, command word.
  • InSR (In-Service Register) : It is used to store all interrupt levels currently being serviced. Each bit of this register is set by priority resolver and reset by end of interrupt command word. The microprocessor can read contents of this register by issuing appropriate command word.
  • IMR (Interrupt Mask Register) : It is a programmable register. It is used to mask unwanted interrupt request, by writing command word. The microprocessor can read contents of this register without issuing any command word.
  • Priority resolver : It determines the priorities of the bit set in the IRR. To make decision, the priority resolver looks at the ISR. If the higher priority bit in the InSR is set then it ignores the new request. If the priority revolvers finds that the new interrupt has a higher priority than the highest priority interrupt currently being serviced and the new interrupt is not in service, then it will set appropriate bit in the InSR and send the INT signal to the microprocessor for new interrupt request.

Discuss 8237 DMA controller in detail.


Discuss 8237 DMA controller in detail.

       The 8237 DMA Controller : 8237 is a programmable DMA  controller present in 40 pin package. 8237 has a 4 channels with channel capable of transferring 64kb. It must interface with two types of devices : the MPU and peripherals such as floppy disks. As mentioned earlier, the DMA plays two roles in a given system : It is an I/O to the microprocessor (slave mode) and it is a data transfer processor to peripherals such as floppy disks (master mode). Many of its signals that are input in the I/O mode become outputs in the processor mode. It also needs additional signals lines to communicate with the address 64 k data bytes and these signals must be generated externally by using latches and buffers. The 8237 is complex device. To maintain clarity, the following discussion is divided into five segments : DMA channels and interfacing. DMA signals, system interface programming, and DMA execution.
     Block Diagram of 8237 : Figure shows the internal block diagram of 8237. It contains blocks of control logic and internal registers.
The block diagram of 8237 DMA controller
Control Logic : The 8237 A contains three blocks of control logic.
  • Timing Control Block : It generates internal timing and external control signal for the 8237A.
  • Program Command Control Block : It decodes various commands given to 8237A by the microprocessor before servicing a DMA request. It also decodes the 'Mode control word, which is used to select the type of DMA during the servicing.
  • Priority Encoder Block : It resolves the priority between DMA channels requesting services simultaneously.
  • Internal Registers : The 8237 contains 344 bits internal memory in the form of registers.

Write short notes on directives and operators.


Assembler directives : These are the statements that direct the assembler to do something. As the name suggest, it direct the assembler to do a task.
  • The specialty of these statements is that they are effective only during the assembly of a program but they do not generate any code that is machine executable.
  • We can divide the assembler directives into two categories namely the general purpose directives and the special directives.

They are classified into the following categories namely the general purpose directives and the special directives.
  1. Simplified segment directives
  2. Macros related directives.
  3. Segment directives.
  4. Data allocation directives.
  5. Code label directives.
  6. Scope directives.
  7. Listing control directives.
  8. Miscellaneous directives.
Operators : Various operators are as follows :
  1. Length : It is operator which tells the assembler to determine the number of elements in some named data item such as a string or array. Example, MOV BX, LENGTH STRING 1; Loads the length string in BX.
  2. OFFSET : It is an operator which tells the assembler to determine the off set or displacement of a named data item (variable) from the start of the segment which contais. Example, MOV AX, OFFSET MESI, : Loads the offset of variable, MESI in AX register.
  3. Short : A short is an operator. It tells the assembler that only 1 byte displacement is needed to code a jump instruction. If the jump destination is after the jump instruction in the program, the assembler will automatically reserve 2 byte for the displacement. Using the short operator saves 1 byte of memory by telling the assembler that it only needs to reserve 1 byte for this particular jump. The short operator should be used only when the destination is fit the range of 128 bytes of +127 bytes from the address of the instructions after the jump. Example, IMP SHORT NEAR-LABEL
  4. Type : It is an operator which tells assembler to determine the type of specified variable. Assembler determines the type of specified variable in number of bytes. For byte types variable the assembler gives a value of 1. For word type variable the assembler gives a value 2 and for doubles word type variable  the assembler gives a value of 4.

Explain NOP and HLT instructions in 8086 microprocessor in detail.


Explain NOP and HLT instructions in 8086 microprocessor in detail.

NOP instruction :


Mnemonic
NOP : No operation
It does not affect any flag
Algorithm
DO nothing

Addressing Mode
Implied addressing mode


Operation : The execution of this instruction causes the CPU to do nothing.

  1. This instruction causes the CPU to do nothing. This instruction uses three clock cycles and increments the instruction pointer to point to the next instruction.
  2. It can be used to increase the delay of a delay loop.
HLT (Halt until interrupt or reset) Instruction :-

Mnemonic  Halt     Flags : No flags are affected.

Operation :
  1. The HLT instruction will cause the 8086 enters to stop fetching and executing instructions. The 8086 enters into a half state. To come out of the halt state, there are 3 ways given below. (a) Interrupt signal on INTR pin, (b) Interrupt signal on NMI pin, (c) Reset signal on rest pin.
  2. It may be used as an alternative to an endless software loop in situation where a program must wait for an interrupt.

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