What are flag manipulation instructions ? Explain logical instructions in detail.
Flag Instructions (Flag Transfer) : These instructions are related to movement of flag register to/from a register and memory.
Flag Instructions (Flag transfer) :
- LAHF (Load AH register from flags)
- SAHF (Store AH register flags)
- PUSHF (Push flags onto stack)
- POPF (Pop flags off stack)
=> LAHF - Load AH register from flags : Copy lower byte of flag register to AH.
Mnemonic LAHF Flags No flags are affected
Algorithm AH = flag register's lower byte
Addr. Mode Implied Addressing mode
Operation AH <- Lower byte of flag register
The lower byte of 8086 flag register is copied to the AH register.
=> SAHF - Store AH register in Flags : Copy contents of AH to lower byte of flag register
Mnemonic SAHF Flags No flags are affected.
Algorithm AH = flag register
Addr. Mode Implied Addressing mode
Operation AH -> Lower byte of flag register.
- This instruction copies the contents of AH register to the lower byte of flag register.
- It is included for 8085 compatibility.
- The OF, DF, IF and TF are not affected.
=> PUSHF - Push flags onto stack : PUSH flag register on the stack
Mnemonic PUSHF Flags No flags are changed.
Algorithm SP = SP - 2
SS : [SP] (top of stack) = operand.
Addr. Mode Register Addressing mode
Operation SP -> SP -2 SS -> data from flag register
- This instruction decrements the stack pointer by 2 and copies word in the flag register to the memory location pointed by stack pointer.
- The stack segment register is not affected.
=> POPF - Pop flags off stack :
Mnemonic POPF Flags All flags are affected.
Algorithm SS = data to flag register SP = SP + 2
Addr. Mode Register Addressing mode
Operation SS : [SP] -> Copy data to flag register SP = SP + 2.
- This instruction copies a word from the two memory locations at the top of the stack to flag register and increment the stack pointer by 2.
- The stack segment register and word on the stack are not affected.
Logical instructions : 8085 microprocessor provides four instructions to control interrupt logic.
(i) EI (Enable Interrupt) : It is used to enable all maskable interrupts. This instruction sets an INTR flip-flop of interrupt control logic. It is single byte instruction.
It is also used to enable maskable interrupts during execution of ISR. It does not affect on TRAP. The INTE flip-flop is not set during execution of EI instruction. Hence the microprocessor does not accept any maskable interrupt at the end of EI execution. The INTE flip-flop is set during T2 of next machine cycle when a maskable interrupt is activated during execution of EI, the microprocessor completes execution of EI and next instruction before accepting maskable interrupt.
(ii) DI (Disable Interrupt) : It is used to disable all maskable interrupt. This instruction resets an INTE flip-flop of interrupt control logic. It is a signal byte instruction. It requires only one machine cycle (4t). It is also used to prevent a critical part of program from maskable interrupts. It does not affect TRAP. The INTE flip-flop is still set during execution of DI instruction. Hence the microprocessor accepts maskable interrupts at the end of DI execution. The INTE flip flop is reset during T2 of next machine cycle.
(iii) SIM (Set Interrupt Mask) : It is a one byte instruction. It requires only one machine cycle (4T). It is used to enable or disable RST 7.5, RST 5.5 interrupt. It does not affect on TRAP and INTR. It is also used in serial data transmission. It transfers control word or SIM format from accumulator to the interrupt control logic. It also transfers serial data bit (D7) to the SOD Pin. Hence the following control format must be loaded into accumulator before execution of SIM instruction.
(iv) RIM (Read Interest Mask) : It is a single byte instruction, it is used to check status of all maskable interrupts. It also transfers serial data bit from SID line to D7 bit os accumulator. IT does not provide status format automatically after execution of RIM instruction. This instruction is used to check pending interrupts.
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