MENU
Featured

    Featured Posts

What do you mean by Data Structure ? Describe different types of Data Structure ?

Filed Under: , , , , on


Q.1. What do you mean by Data Structure ? Describe different types of Data Structure ?
Ans. Data Structure : A data structure is a class of data that can be characterised by its organization and the operations that are defined on it. Hence
Data Structures = Organised data + Allowed operations

In other words, the organised collection of data is called data structure.
Let us now formally define a Data Structure.
     A data structure is a set of values along with the set of operations permitted on them. It is also required to specify the semantics of the operations permitted on the data values, and this is done by using a set of axioms, which describes how these operations work, and therefore a data structure is made of
  • A set of data values
  • A set of functions specifying the operations permitted on the data values.
  • A set of axioms describing how these operations work.
Classification of Data Structure : There are various ways to classify data structure.
  • Primitive and Non-Primitive data structure :  The data structure that are atomic (indivisible) are called primitive. Example are integer, real, boolean and characters. 
            The data structures that are not atomic are called non primitive or composite. Example are records, array and string.
  • Linear and Non-Linear data structure : In a linear data structure, the data items are arranged in a linear sequence. Example is array. 
      In a non-linear data structures, the data items are not in sequence. Example is tree.
  • Homogeneous and Non-Homogeneous data structure : In homogeneous structures, all the elements are of same type. Example is arrays.
      In non-homogeneous structures, the elements may or may not be of the same type. Example is Records.
  • Static and dynamic data structures : Static structures are ones whose size and structures, associated memory location are fixed at compile time.
      Dynamic structures are ones which expand or shrink as required during the program execution and there associate memory location change.
 
Read more

Write Reverse algorithm for binary search.

Filed Under: , , , on


Write Reverse algorithm for binary search.

     The Reverse method reverses the order of the elements in an array.
    BinarySearch(): performs a binary search on the list of elements.
    Sort(): Sorts the items
    Reverses items
{

int mid;
int first = 0;
int last = list.length(-) - 1;
while ( first <= last )
{
mid = (first + last)/2;
if ( list[mid] == target )
return mid;
if ( list[mid]>target )
last = mid - 1;
else
first = mid + 1;
}
return - 1;
}
Sorting :{
Intmain()
Intarray[] = {};
Int elements = sizeof(array);
Std::sort(array,array + elements);
For(int=0, i<<elements, i++)
Std::cout<<array[i]<<' ';
}
Reverse the array:
{
int n,c,t,end,array[];
for(c=0, c<n/2, c++)
{
t = array[c];
array[c] = array[end];
array[end] = t;
}
Read more

Explain direct memory access.

Filed Under: , , , on

Explain direct memory access.

       Direct memory access (DMA) :- It is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit(CPU).
     Without DMA, when the CPU is using programmed input/output, it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU initiates the transfer, does other operations while the transfer is in progress, and receives an interrupt from the DMA controller when the operations is done. This feature is useful any time the CPU cannot keep up with the rate of data transfer, or where the CPU needs to perform useful work while waiting for a relatively slow I/O data transfer. Many hardware systems use DMA, including disk drive controllers, graphics cards, network cards and sound cards. DMA is also used for intra-chip data transfer in multi-core processors. Computers  that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without DMA channel. Similarly, a processing element inside a multi core processor can transfer data to and from its local memory without occupying its processor time, allowing computation and data transfer to proceed in parallel.
Read more

What is programmable interval timer ?

Filed Under: , ,

What is programmable interval timer ?

      There are two types of programmable interval timer are generally used. Intel 8253 is a programmable Interval Timer/Counter which can generate accurate time delays and wave forms ranging from 0 HZ to 2 MHz using software control. 8254 is its upgraded version which can operate with higher clock frequency range (DC - 8 MHz) and it is pin to pin compatible with 8253.

Read more

What are NOP and HLT instructions ?

Filed Under: , , , on


What are NOP and HLT instructions ?

 NOP Instruction :

 Mnemonic      NOP           Flags : It does not affect any flag.
                    NOP : No operation
Algorithm      Do nothing
Addr. mode    Implied addressing mode
Operation      The execution of this instruction causes the CPU to do nothing.

  1. This instruction causes the CPU to do nothing. This instruction uses three clock cycles and increments the instruction pointer to point to the next instruction.
  2. It can be used to increase the delay of a delay loop.
Example : 
MOV AL, 00011011b
NOT AL ; AL = 11100100b
RET
Flags : All unchanged.

HLT (Halt until interrupt or reset) Instruction :

Mnemonic      Halt processing           Flags : No flags are affected.

Operation :
  1. The HLT instruction will cause the 8086 to stop fetching and executing instructions. The 8086 enters into a half state. To come out of the halt state, there are 3 ways : (a) Interrupt signal on INTR pin, (b) Interrupt signal on NMI pin, (c) Reset signal on reset pin.
  2. It may be used as an alternative to an endless software loop in situations where a program must wait for an interrupt.
Read more

Write a program to find 1's complement of the number.

Filed Under: , , ,


Write a program to find 1's complement of the number.

       Statement : Find the 1's complement of the number stored at memory location 2200H and store the complemented number at memory location 2300H.
Sample problem:
(2200H) = 55H
Result = (2300H) = AAH

 Program :

LDA 2200H -> Get the number
CMA -> Complement number
STA 2300H -> Store the result
HLT -> Terminate program execution.
 
Read more

Microprocessing and Interfacing Dec 2016 sample paper Code-EE-309-F

Filed Under: , , , ,


Microprocessing and Interfacing
Dec 2016
Paper Code-EE-309-F

Q.1

Q.2

Q.3
(b) What is the functioning of timing and control unit in 8085 microprocessor? Discuss all its signals in details.

Q.4
(b) Discuss Pipelining .

Q.5
(b) How physical address is computed in 8086 microprocessor ?

 Q.6. Write a simple assembly program to subtract two memory location, where each memory location is one byte wide.

Q.7
(a) Write short notes on directives and operators.
(b) Write a 8086 assembly language program to find largest number in data array.

 Q.8. Explain 8259 interrupt controller with the help of block diagram.

Q.9. Explain the following :
(a) 8253/8254 programmable interval timer.
(b) Instruction register and priority resolver.
Read more

Explain 8259 interrupt controller with the help of block diagram.

Filed Under: , , , on

Explain 8259 interrupt controller with the help of block diagram.

    It contains following blocks :
Functional block diagram of 8259 interrupt controller


  • Data bus buffer : It is used to transfer data between microprocessor and internal bus.
  • Control logic : It generates an INT signal. In response to an INTA signal, it releases three byte CALL address or one byte vector number. It controls read/write control logic, cascade buffer/comparator, in service register, priority resolver and IRR.
  • Cascade buffer and comparator : In master mode, it functions as a cascaded buffer. The cascaded buffers outputs slave identification number on cascade lines. In slave mode, it functions as a comparator. The comparator reads slave identification number from cascade lines and compares this number with its internal identification number. In buffered mode it generates an EN signal.
  • Read/write logic : It sets the direction of data bus buffer. It controls all internal read/write operations. It contain initialisation and operation command register.
  • IRR(Interrupt Request Register) : It is used to store all pending interrupt requests. Each bit of this register is set at the rising edge or at the high level of the corresponding interrupt request line. The microprocessor can read contents of this register by issuing appropriate, command word.
  • InSR (In-Service Register) : It is used to store all interrupt levels currently being serviced. Each bit of this register is set by priority resolver and reset by end of interrupt command word. The microprocessor can read contents of this register by issuing appropriate command word.
  • IMR (Interrupt Mask Register) : It is a programmable register. It is used to mask unwanted interrupt request, by writing command word. The microprocessor can read contents of this register without issuing any command word.
  • Priority resolver : It determines the priorities of the bit set in the IRR. To make decision, the priority resolver looks at the ISR. If the higher priority bit in the InSR is set then it ignores the new request. If the priority revolvers finds that the new interrupt has a higher priority than the highest priority interrupt currently being serviced and the new interrupt is not in service, then it will set appropriate bit in the InSR and send the INT signal to the microprocessor for new interrupt request.
Read more

Discuss 8237 DMA controller in detail.

Filed Under: , , ,

Discuss 8237 DMA controller in detail.

       The 8237 DMA Controller : 8237 is a programmable DMA  controller present in 40 pin package. 8237 has a 4 channels with channel capable of transferring 64kb. It must interface with two types of devices : the MPU and peripherals such as floppy disks. As mentioned earlier, the DMA plays two roles in a given system : It is an I/O to the microprocessor (slave mode) and it is a data transfer processor to peripherals such as floppy disks (master mode). Many of its signals that are input in the I/O mode become outputs in the processor mode. It also needs additional signals lines to communicate with the address 64 k data bytes and these signals must be generated externally by using latches and buffers. The 8237 is complex device. To maintain clarity, the following discussion is divided into five segments : DMA channels and interfacing. DMA signals, system interface programming, and DMA execution.
     Block Diagram of 8237 : Figure shows the internal block diagram of 8237. It contains blocks of control logic and internal registers.
The block diagram of 8237 DMA controller
Control Logic : The 8237 A contains three blocks of control logic.
  • Timing Control Block : It generates internal timing and external control signal for the 8237A.
  • Program Command Control Block : It decodes various commands given to 8237A by the microprocessor before servicing a DMA request. It also decodes the 'Mode control word, which is used to select the type of DMA during the servicing.
  • Priority Encoder Block : It resolves the priority between DMA channels requesting services simultaneously.
  • Internal Registers : The 8237 contains 344 bits internal memory in the form of registers.
Read more

Describe various branch instructions in 8086 microprocessor.

Filed Under: , , , on

Describe various branch instructions in 8086 microprocessor.

Various branch instructions are as follows :
(i) Jump Instructions : This group of instructions will always cause the 8086 to fetch its next instruction from the location specified or indicated by instruction rather that from the next location after the JMP instruction. The JMP instructions are basically classified as unconditional jump and conditional jump instructions. A conditional jump instruction allows the programmer to make decisions based upon numerical tests. The results of numerical tests are held in the flag bits, which are then tested by conditional jump instructions.

     The jump instructions are further classified as short, near and far jump instructions.
Short  
EB
Disp

Near
Opcode
E9
Disp Low
Disp High

Far
Opcode
EA
IP Low
IP High
CS Low
CS High

(ii) Call Instructions : The CALL instruction differs from the JMP instruction because a call instruction saves the return address on the stack. On execution of the RET instruction, the program returns to the place where the CALL was enabled. It is 2 types, namely, near CALL and Far Call.

       Near Call : It is 3 byte instruction with 1st byte containing the opcode and 2nd and 3rd byte containing the 16 bit displacement. Example OFFFH, this identical to the form of near jump. 

       Far Call : The far call is like far jump. It is 5 byte instruction.

 (iii) Interrupt Instruction : 

  • Int Instruction (INT type) : This instruction causes the 8086 to call a far procedure. The term type in the instruction refers to a number between 0-255 which identifies the interrupt. The address of the procedure is taken from the memory whose address is four times the type number.
  • INTO Instruction : If the overflow flag is set, this instruction will cause the 8086 to do an indirect far call to a procedure you write to handle overflow condition. To do call the 8086 will read a new value or IP from address 000 10H and a new value of CS from address 000 12H.
  • IRET Instruction : The IRET instruction is used at the end of the interrupt services routine to return execution to the interrupt program. The 8086 copies return address from stack into IP and CS registers and the stored value of flags back to the flag register.
Read more

What are flag manipulation instructions ? Explain logical instructions in detail.

Filed Under: , , ,

What are flag manipulation instructions ? Explain logical instructions in detail.

Flag manipulation instruction of 8086 :-

Flag Instructions (Flag Transfer) : These instructions are related to movement of flag register to/from a register and memory.

Flag Instructions (Flag transfer) :

  1. LAHF (Load AH register from flags)
  2. SAHF (Store AH register flags)
  3. PUSHF (Push flags onto stack)
  4. POPF (Pop flags off stack)
=> LAHF - Load AH register from flags : Copy lower byte of flag register to AH.

Mnemonic       LAHF       Flags       No flags are affected
Algorithm        AH = flag register's lower byte
Addr. Mode     Implied Addressing mode
Operation        AH <- Lower byte of flag register 
                        The lower byte of 8086 flag register is copied to the AH register.
=> SAHF - Store AH register in Flags : Copy contents of AH to lower byte of flag register

Mnemonic       SAHF          Flags      No flags are affected.
Algorithm         AH = flag register
Addr. Mode      Implied Addressing mode
Operation         AH -> Lower byte of flag register.
  • This instruction copies the contents of AH register to the lower byte of flag register.
  • It is included for 8085 compatibility.
  • The OF, DF, IF and TF are not affected.
=> PUSHF - Push flags onto stack : PUSH flag register on the stack

Mnemonic       PUSHF           Flags        No flags are changed.
Algorithm        SP = SP - 2
                       SS : [SP] (top of stack) = operand.
Addr. Mode     Register Addressing mode
Operation        SP -> SP -2        SS -> data from flag register
  • This instruction decrements the stack pointer by 2 and copies word in the flag register to the memory location pointed by stack pointer.
  • The stack segment register is not affected.

=> POPF - Pop flags off stack : 

Mnemonic     POPF                 Flags         All flags are affected.
Algorithm       SS = data to flag register    SP = SP + 2
Addr. Mode    Register Addressing mode
Operation       SS : [SP] -> Copy data to flag register        SP = SP +  2.
  1. This instruction copies a word from the two memory locations at the top of the stack to flag register and increment the stack pointer by 2.
  2. The stack segment register and word on the stack are not affected.
Logical instructions : 8085 microprocessor provides four instructions to control interrupt logic.

(i) EI (Enable Interrupt) : It is used to enable all maskable interrupts. This instruction sets an INTR flip-flop of interrupt control logic. It is single byte instruction. 
      It is also used to enable maskable interrupts during execution of ISR. It does not affect on TRAP. The INTE flip-flop is not set during execution of EI instruction. Hence the microprocessor does not accept any maskable interrupt at the end of EI execution. The INTE flip-flop is set during T2 of next machine cycle when a maskable interrupt is activated during execution of EI, the microprocessor completes execution of EI and next instruction before accepting maskable interrupt.

(ii) DI (Disable Interrupt) : It is used to disable all maskable interrupt. This instruction resets an INTE flip-flop of interrupt control logic. It is a signal byte instruction. It requires only one machine cycle (4t). It is also used to prevent a critical part of program from maskable interrupts. It does not affect TRAP. The INTE flip-flop is still set during execution of DI instruction. Hence the microprocessor accepts maskable interrupts at the end of DI execution. The INTE flip flop is reset during T2 of next machine cycle.

(iii) SIM (Set Interrupt Mask) : It is a one byte instruction. It requires only one machine cycle (4T). It is used to enable or disable RST 7.5, RST 5.5 interrupt. It does not affect on TRAP and INTR. It is also used in serial data transmission. It transfers control word or SIM format from accumulator to the interrupt control logic. It also transfers serial data bit (D7) to the SOD Pin. Hence the following control format must be loaded into accumulator before execution of SIM instruction.

(iv) RIM (Read Interest Mask) : It is a single byte instruction, it is used to check status of all maskable interrupts. It also transfers serial data bit from SID line to D7 bit os accumulator. IT does not provide status format automatically after execution of RIM instruction. This instruction is used to check pending interrupts.
Read more

Describe various arithmetic instructions with examples in 8085 microprocessor.

Filed Under: , , ,

Describe various arithmetic instructions with examples in 8085 microprocessor.

 The arithmetic group of instruction include following instructions :
ADD R
ACI data
SBB M
DCR R
ADD M
DAD Rp
SUI data
DCR M
ADC R
SUB R
SBI data
INX Rp
ADC M
SUB M
INR R
DCX Rp
ADI data
SBB R
INR M
DAA
Some of the describe as follows :

 ADD R :
Description : Add register R contents to accumulator. This instruction adds the contents of register R and accumulator and stores the result in accumulator. The example of R are all general purpose register such as A, B, C, D, E, H and L. In addition to the result in accumulator all the flags are modified to reflect the result of operation.

 Operation : A + R -> A
example :  ADD : A + B -> A. Suppose A = 40 H and B = 65 H.
  A 0100 0000
+B 0110 0101
  A 1010 0101

 ADC R :
Description : Add register cut carry flag contents to accumulator. This instruction adds the contents of register R, Carry flag CY and accumulator and stores the result in accumulator. The example of R are all general purpose registers such as A, B, C, D, E, H and L. In addition to the result in accumulator all the flags are modified to reflect the result of operation.
Operation : A + R -> Cy -> A
Example : ADC : A + B + Cy -> A.
Suppose b = 20, A = 3 F and Cy = set and ADC B is instruction is executed.
A = 0011 1111
B = 0011 0000
Cy = 
A = 0110 0000

ADI data :
Description : Add immediate data to accumulator. This instruction adds the 8 bit data specified along with the instruction to accumulator and result is stored in accumulator. All flags are also modified to reflect the result of operation. The storing format of this instruction will be 1st byte opcode and 2nd byte operand (data).
Operation : A + data -> A
Example : ADI B7 H : add B7 H data to accumulator and store result in accumulator. Suppose A = 59 H instruction ADI B7 is executed
A = 0101 1001
M = 1011 0111
     10110 0000

 DAD Rp :
Discription : This instruction adds the contents of specified register pair to HL pair and stores the result in HL pair. The example of Rp are SP, BC, DE and HL. Only carry flag is modified to reflect the result operation
Operation : Rp + HL -> HL
Example : (i) DAD B : BC + HL -> HL
(ii) DAD SP : SP + HL -> HL
  DAD B
Suppose B = 21, C = 45,, H = 80, L = 35, is executed.
 2145 BC
+8035 HL
  A17A HL

 SUB M :
Description : Subtract memory location contents from accumulator. This instruction subtracts memory location contents from accumulator and result is placed in accumulator. The subtraction is performed in the same ways as SUB R instruction. All flags are modified to reflect the result of operation.
Example : SUB M : A - (HL) -> A.
Suppose A = 50H, H = C2, L = 00, at memory location C200 : 20 H is stored and instruction SUB M is executed.
(C200)= 0010 0000
2's com = 1110 0000
       A = 0101 0000
2's cop. = 1110 0000
           [1] 0011 0000

 SUI data :
Description : Subtract immediate data from accumulator.
This instruction subtracts the data specified along with instruction from accumulator. The subtraction is performed by using 2's complement method and operation is same as SUB R instruction.
Operation : A - data -> A
Example : SUI 50 : A - 50 -> A.
Suppose A = 20 and instruction SUI 50 is executed.

 INR M :
Description : Increment memory contents by one. This instruction increments the contents of memory location address by HL register pair by 1 and result is stored back at the same memory location. Only carry flag is not modified, all other flags are modified.
Operation : (HL0 + 1 or M + 1 -> M
Example : INR M : (HL) + 1 -> (HL).
Suppose H = C2, L = 02, at memory location C202 : 04 is stored, flag reg = 10 *1*0*1 and instruction INR M is executed.
Read more

Describe the architecture of 8085 micro-processor.

Filed Under: , , , on

Describe the architecture of 8085 micro-processor.

        Architecture of 8085 microprocessor : The figure below shows the architecture of 8085 microprocessor. We divide the architecture in different in different groups as follows :-
The 8085A Microprocessor : Functional block diagram

(i) Arithmetic and Logical Group : This group consists of ALU, accumulator, temporary register and flags register.

  • ALU : The ALU performs arithmetic and logical operations such as addition, subtraction, ANDing, ORing, EXORing etc.
  • Accumulator : The accumulator is a 8 bit general purpose register connected to internal data bus and a ALU.
  • Temporary Register : The other input to ALU is given by temporary register. This register is not available for user. It is only used internally by microprocessor, so the name given temporary register.
  • Fla Register : The flag is nothing but a group of flip-flops used to give status of different operations result.
(ii) Register Group : This group consists of 3 types of register :
  • Temporary registers (W & Z) : These are not available for user and are used only for internal operations such as to store operand immediately or address of memory. These are used internally by microprocessor only to store 8 bit data/information required for execution of certain instructions.
  • General Purpose registers : The 8085 contains 6 general purpose register of 8 bits each named as B, C, D, E, H and L. These can be used to store 8 bits or can be used to form a register pair to store 16 bits. The register pairs available are BC, DE and HL. These register are programmable by user. User can store any data in these registers and use it to perform different operations.
  • Special purpose registers : The 8085 contains 3 special purpose registers such as program counter incrementer/decrementer latch and stack pointer.
(iii) Interrupt Control : This block accepts different interrupt request inputs such as TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR and informs control logic to take action in response to each signal. The response for TRAP, RST 7.5, RST 6.5 and RST 5.5 is CALL at restart address. But for INTR it generates a signal INTA and excepts external device should insert a RST code or CALL instruction.

(iv) Serial I/O Control group : The data transferred on D0 to D7 lines is parallel data, but under certain condition it is advantageous to use serial data transfer. 8085 implements this by using SID and SOD signal and the data on these lines is accepted or transferred under software control by serial I/O control block, by using special instructions RIM and SIM.

(v) Instruction Register, Decoder and Control Group :
  • Instruction Register : When an instruction is fetched from memory it is loaded in instruction register form there it is provided to decoder for decoding. This register is only activated when a instruction code or Opcode is available on internal data bus. It is non-programmable register, i.i not available for programmers use. Remember it accepts only opcode of instructions, operands are not accepted by this instead they are stored in registers.
  • Instruction Decoder : This accepts a bit pattern from instruction register decodes it and gives the decoded information to control logic. The information includes what operation is to be performed, who is going to perform it, how many operand bytes the instruction contains etc.
  • Timing and Control : This is a control section of 8085 microprocessor. This accept information from instruction decoder and generates micro steps to perform it, so 8085 is called as micro-programmed. In addition to this the block accepts clock inputs and performs sequencing and synchronizing operations required for communication between microprocessor and peripheral devices.

Read more

What are control and status signals? Explain them

Filed Under: , , ,

What are control and status signals? Explain them.

        Various type of control and status signals are as follows :

 (i). Address latch enable (ALE) :-

  • This is an output signal, used to give information of AD0 -AD7 contents.
  • It is a positive going pulse generated during the first clock cycle of a machine cycle.
  • When pulse is high it indicates that the contents of AD0 - AD7 are address. When it is low it indicates that the contents are data.
  • The ALE signal is used to separate AD0 -AD7 (i.e demultiplex) to A0 - A7 and D0 - D7. To do this separation an external latch is connected to AD0 - AD7 lines and this latch is controlled by ALE signals.
(ii) Input output/memory (IO/M) : 
  • This is an output status signals, used to give information of operation to be performed with memory or I/O device.
  • If IO/M = 0, the microprocessor is performing a memory related operation.
  • If IO/M = 1, the microprocessor is performing an I/O device related operation.
(iii) Read (RD) : 
  • This is an active low signal.
  • It is an output control signal that is used to read data from the selected memory location or an I/O location via data bus.
(iv)  Write (WR) :
  • This an active low signal.
  • It is an output control signal used to write data to selected memory location or an I/O location via data bus.
  • A low on this pin indicated that a operation performed is write operation.
(v) Status signal (S1 and S2) :
  • These are output status signals used to give information of operation performed by microprocessor.
  • When S0 and S1 is combined with IO/M we get status of all the machine cycles (operations) performed by 8085 as shown in table below :
Table
Status signals
Operation
Control signal used
IO/M
S1
S2


0
0
0
-
-
0
0
1
Memory write
WR
0
1
0
Memory read
RD
0
1
1
Opcode fetch
RD
1
0
0
-
-
1
0
1
I/O write
WR
1
1
0
I/O read
RD
1
1
1
Interrupt acknowledge
INTA
Z
0
0
Halt

Z
X
X
Hold

Z
X
X
Reset

Where : Z – Tristate ( High impedance condition ) X- Unspecified condition

(vi) Ready : 
  • This is an active high input control signal.
  • It is used by microprocessor to detect whether a peripheral is ready for the data transfer or not. If not the processor waits till the signal goes high.
  • The main function of this pin is to synchronization the microprocessor 8085 with slower peripherals i.e. the microprocessor waits till the peripherals is not ready to accept/send the data.
Read more

www.CodeNirvana.in

www.posthatke.com. Powered by Blogger.
Copyright © www.posthatke.com | Blogger Templates | Designed By posthatke.com