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Explain the working of 8255 in mode 2 and BSR Mode. Also explain how the contents of control registers are interpreted in BSR and I/O mode.



Explain the working of 8255 in mode 2 and BSR Mode.  Also explain how the contents of control registers are interpreted in BSR and I/O mode.

     Working of 8255 in mode 2 : In this mode group A is used as input and output i.e. for transmitting and receiving  data from peripheral through 8255.
        As shown in figure, the transfer of data is achieved by port C handshake signals. The group B can be in Mode 0 or Mode 1.
       The bi-directional data is transferred through port A so it consists of input and output latch.
       The Mode 2 is combination of Mode 1 input output both at a time to port A.
       The interrupt signals of input and output mode are combined to generate common interrupt signal to CPU. The internal organization of these signals, which is shown in figure 2.
       The different handshake signals used are OBFa, ACKa, STBa, IBFa and INTERa handshake signals are used for output operation, 2 are used for input operation and one is common to both.

     Output operation :
Pa, Pb and Pc in mode 2

     OBF (Output buffer full) : This is an active low output signal generated by 8255. When CPU write data to output port 8255 will enable OBF signal to indicate peripheral that data is available in output buffer.

     ACK (Acknowledge) : This is an active low input signal for 8255. When the peripheral detects OBF signal, it reads data from 8255 port and makes ACK = 0 and the ACK signal is used to acknowledge 8255 that data is read from port so 8255 will remove OBF signal to indicate output buffer is empty.

   Input operation :

     STB (strobe) :  This is an active low input signal. When the peripheral writes data to input buffer, it generates a signal STB to indicate 8255 that it has written data.
     IBF (Input buffer full) : When data is available in input buffer 8255 will enable IBF signal to indicate that data is available in input buffer.

     INTR (Interrupt request) : This is an output signal given by 8255 to request CPU service.

     The INTR is generated in two different conditions input and output.
     The interrupt is generated for input mode when IBF = 1, STB = 1, and INTE1 = 1 and for putput mode when OBF = 1, ACK = 1, and INTE2 = 1. The INTE1 and INTE2 are set/reset using BSR mode, port C bits used are PC6 and PC4 respectively.
      The logical equation will be,
       INTRa = INTE1.ACKa.OBFa. + INTE2.STBa.IBFa

      The timing diagram of Mode 2 bi-directional data transfer for data transfer from peripheral to CPU and CPU to peripheral are shown in figure below :

The mode 2 also supports both modes of data transfer i.e. Interrupt drive I/O and status driven I/O. The port C is used as status word and its definitions are as follows :

            OBFa  INTE1  IBFa    INTE2       INTRa     X         x             x


Timing diagram of mode 2 in 8255
       Working of 8255 in BSR :  The BSR is a Port C bit set reset mode. The mode used eight bits of Port C only. The individual bit of Port C can be set or reset by writing control word in the control register.
       The control word format of BSR mode is as shown in figure and mode selection formal is in figure 2.

Figure 1
       The pin of Port C, i.e. bit 0 to bit 7 to set or reset is chosen using bit select bits, b3b2b1, i.e. D3, D2 and D1 of control word register. The bit to set or reset is decided by bit S/R, i.e. D0. The BSR mode affects only one bit of Port C at a time. The bit set using BSR mode remains set unless and until you change the bit. The bit to be set/reset is decided by control word. So to set any bit of Port C, bit pattern is loaded in control register. Even though a BSR mode is selected it will not affected I/O mode.

     Control Word :

Figure 2 Control word
 

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