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Explain the purpose of EU and BIU in 8086 microprocessor


Explanation of the purpose of EU and BIU in 8086

     Bus Interface Unit (BIU) : The  BIU interface 8086 to outside word. It provides full 16 bit bidirectional data bus and 20 bit address bus. The BIU is responsible for performing all external bus operations as given below : 

  1. It sends address of the memory or I/O.
  2. It fetches instruction from memory.
  3. It reads data from port/memory.
  4. It writes data into port/memory.
  5. It supports instruction queuing.
  6. It provides the address location facility.
      The BIU has a dedicated order. The main function of this order is to produce 20 bit physical address. The bus control logic of the BIU generates all bus control signals such as READ and WRITE for memory and I/O.

       Instruction Queue : To speed up program execution, the BIU fetches six instruction bytes ahead of time from memory. These prefetched instruction bytes are held for the execution unit in a group of registers called queue. With the help of queue it is possible to fetch next instruction while current instruction is in execution. There are number of instructions in 8086 microprocessor which need a quite large number of clock cycles for execution. During this execution time the BIU fetches the next instruction or instructions from memory into the instruction queue instead of remaining idle. Th BIU continues this process as long as the queue is not full. Due to this execution unit gets, the ready instructions in the queue and instruction fetch time is eliminated ( while decoding or executing an instruction EU does not require use of the buses).

       This system has the advantage over the 8085 microprocessor because, while EU is executing an instruction, the BIU is fetching and storing in the queue the next instructions.
       The BIU's instruction queue is based on first in first out (FIFO). So that the EU gets the instructions for execution in the order they are fetched. If the queue is full and EU does not request BIU for accessing memory, the BIU does not perform any bus cycle. On the other hand, if the queue is not full and even through the EU does not request BIU for accessing the memory the BIU can fill the queue on its own. If the EU interrupts the BIU, the BIU 1st completes the prefetching and then attains to the service of the EU.

       In case of JUMP and CALL instruction, instruction already fetched in queue are of no use. Hence, in these cases queue is dumped and newly formed by loading instructions from new address specified by JUMP and CALL instruction.

       Execution Unit (EU) :  The EU of 8086 tells the BIU from where to fetch instructions or data, decodes instruction and executes instructions. It contains :

  1. Control Circuitary
  2. Instruction Decoder
  3. Arithmetic Logic Unit (ALU)
  4. Flag register
  5. General purpose registers.
  6. Pointers and Index registers.
         The central circuitry in the EU directs the internal operation. A decoder in the EU translates the instructions fetched from memory into a series of actions which the EU performs. ALU is 6 bit. If can add, subtract, AND, OR, XOR, increment, decrements, complement and shift binary numbers
         In the beginning the CS :IP is loaded with the required address from which the execution is to be started. In the initial condition the queue will be empty and the microprocessor starts a fetch operation to bring one byte ( the first byte) of instruction code, if the CS : IP address is odd, and two bytes at a time, if the CS : IP address even. The first byte is a complete opcode in case of some instructions (one byte opcode instructions), the remaining part of opcode may lie in the second byte. But invariably the first byte of an instruction is an opcode. These opcodes along with data are fetched and arranged in the queue. When the first byte from the queue goes for decoding and interpretation, one byte in the queue becomes empty and subsequently the queue is up dated.
  • The microprocessor does not perform the next fetched operation till at least two bytes of the instruction queue are emptied. The instruction execution cycle is never broken for fetch operation. After decoding the first byte the decoding circuit decides whether the instruction is of single opcode byte or double opcode byte. If the single opcode bytes, the next bytes are treated as data bytes depending upon the decoded instruction length. Otherwise, the next byte in the queue is treated as the second byte of the instruction opcode.
  • The queue is updated after every byte is read from the queue but the fetch cycle is entreated by BIU only if at least two bytes of the queue are empty and the EU may be concurrently executing the fetched instructions. 
     The queue operation is shown in the figure below :
Queue operation 

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