Explain Opcode Fetch machine cycle of 8085 microprocessor with the help of timing diagram.
The 8085 uses this cycle to fetch instruction OPCODE from memory.
- In this case, the address of memory is always given by programming counter. The programmer counter is incremented by one to point to the next location.
- There are 2 bytes of OPCODE fetch cycles, one using 4 T states to complete the operation and other using 6 T states to complete the operation. Generally instructions uses 4 T states but some instructions performing some additional operation in OPCODE fetch requires 6 T states.
Figure 1 :
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| Timing diagram of opcode Fetch cycle of 8085 |
Operations :
1. Step 1 (state T1) : In the state 8085 sends the status signals, IO/M.S1 and IO/M = 0. S0 = 1 and S1 = 1.
- The 8085 sends a 16 bit address on A8 - A15 and AD0 - AD7.
- The high order byte of program counter is placed on the A8 - A15 lines and it remains there upto T3 state. The low order byte of program counter is placed on the AD0 - AD7 line which remains there only for T7.
- During this state, ALE (address latch enable ) gives a positive pulse which represents the contents of AD0 - AD7 as an address. The ALE signal is used to latch the address to A0 - A7.
- No control signal is general in state.
2. Step 2 (state T2) : The contents of PCL(Lower order address bus) will disappear on AD0 - AD7 lines, so that the same lines can be used as data lines. The contents of A0 to A7 are still available for memory from external latch.
- The control signal RD(bar) is made LOW by the processor which enables the read circuit of addressed memory device. The memory device then sends the contents on data bus i.e AD0 - AD7.
- In addition to these operations, microprocessor increments PC contents by 1.
3. Step 3 (State T3) : During this clock cycle, the data from memory i.e OPCODE is transferred to instruction register and RD control signal is made HIGH. Thus RD disables the memory device.
4. Step 4 (State T4) : The microprocessor performs only internal operation. The OPCODE is decoded by the CPU and upon decoding 8085 knows all the information about :
- Whether it should enter T5 and T6 states or not.
- How many bytes of instruction it is ?
If the instruction does't require T5 and T6 states, it will start or go to the next machine cycle. If it is multi byte instruction the operand fetch cycles are executed to complete the instruction fetching.
5. Step 5 (T5 and T6) : T5 and T6 states are required to complete decoding and some operations inside the 8085. Operation performed depends on instruction.
NOTE : Following instructions require T5 and T6 states :
Instructions
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Operation
Performed
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CALL
|
Stack pointer is decremented by 1
|
CALL conditional
|
Stack pointer is decremented by 1
|
DCX Rp
|
Register pair decremented by 1
|
INX Rp
|
Register pair incremented by 1
|
PCHL
|
HL pair transferred to PC
|
PUSH RP
|
Stach pointer is decremented by 1
|
SPHL
|
HL pair transferred to SP
|
RET conditional
|
The condition of flags checked.
|
All other instruction except the above instructions require OPCODE fetch of T1 to T4 - $T states only.
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2 comments
Great explaination. Keep it up.
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