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Describe the architecture of 8085 micro-processor.

Describe the architecture of 8085 micro-processor.

       Architecture of 8085 microprocessor : The figure below shows the architecture of 8085 microprocessor. We divide the architecture in different in different groups as follows :-
The 8085A Microprocessor : Functional block diagram

(i) Arithmetic and Logical Group : This group consists of ALU, accumulator, temporary register and flags register.

  • ALU : The ALU performs arithmetic and logical operations such as addition, subtraction, ANDing, ORing, EXORing etc.
  • Accumulator : The accumulator is a 8 bit general purpose register connected to internal data bus and a ALU.
  • Temporary Register : The other input to ALU is given by temporary register. This register is not available for user. It is only used internally by microprocessor, so the name given temporary register.
  • Fla Register : The flag is nothing but a group of flip-flops used to give status of different operations result.
(ii) Register Group : This group consists of 3 types of register :
  • Temporary registers (W & Z) : These are not available for user and are used only for internal operations such as to store operand immediately or address of memory. These are used internally by microprocessor only to store 8 bit data/information required for execution of certain instructions.
  • General Purpose registers : The 8085 contains 6 general purpose register of 8 bits each named as B, C, D, E, H and L. These can be used to store 8 bits or can be used to form a register pair to store 16 bits. The register pairs available are BC, DE and HL. These register are programmable by user. User can store any data in these registers and use it to perform different operations.
  • Special purpose registers : The 8085 contains 3 special purpose registers such as program counter incrementer/decrementer latch and stack pointer.
(iii) Interrupt Control : This block accepts different interrupt request inputs such as TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR and informs control logic to take action in response to each signal. The response for TRAP, RST 7.5, RST 6.5 and RST 5.5 is CALL at restart address. But for INTR it generates a signal INTA and excepts external device should insert a RST code or CALL instruction.

(iv) Serial I/O Control group : The data transferred on D0 to D7 lines is parallel data, but under certain condition it is advantageous to use serial data transfer. 8085 implements this by using SID and SOD signal and the data on these lines is accepted or transferred under software control by serial I/O control block, by using special instructions RIM and SIM.

(v) Instruction Register, Decoder and Control Group :
  • Instruction Register : When an instruction is fetched from memory it is loaded in instruction register form there it is provided to decoder for decoding. This register is only activated when a instruction code or Opcode is available on internal data bus. It is non-programmable register, i.i not available for programmers use. Remember it accepts only opcode of instructions, operands are not accepted by this instead they are stored in registers.
  • Instruction Decoder : This accepts a bit pattern from instruction register decodes it and gives the decoded information to control logic. The information includes what operation is to be performed, who is going to perform it, how many operand bytes the instruction contains etc.
  • Timing and Control : This is a control section of 8085 microprocessor. This accept information from instruction decoder and generates micro steps to perform it, so 8085 is called as micro-programmed. In addition to this the block accepts clock inputs and performs sequencing and synchronizing operations required for communication between microprocessor and peripheral devices.

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