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Describe 8086 Microprocessor architecture with its block diagram.


Describe 8086 Microprocessor architecture with its block diagram.

The 8086 is divided into two functional independent parts :



  1. BIU ( BUS Interface Unit )
  2. EU ( Execution Unit )
     Dividing the work between two unit speed up the processing.  The 8086 and the 8088 differs in their architecture of the BIU. The 8088 BIU provides 8-bit data path instead of 16-bit data path for 8086. EU is same for both the processor.

BIU :  Bus Interface Unit sends out address, fetches instruction from memory, reads data from port and memory and write data to ports and memory. In other words the BIU handles all transfer of data and address on the buses for EU. The following describe the function parts of the BIU :
  1. Instruction Queue
  2. Segment Registers
  3. Instruction Pointer
  4. Bus Interface and memory addressing Logic.
(a). Instruction Queue : The instruction queue is a first-in-first-out group of registers. To speed up program execution, the BIU fetches as many as six instruction bytes are held for the execution unit in a instruction Queue. The IU can be fetching instruction bytes while the Execution Unit is decoding the instruction or executing an instruction which does not require use of the buses. When the Execution Unit is ready for its next instruction, it simply reads the instruction from the instruction Queue in the BIU. This scheme is much faster than sending out an address to memory and then waiting for memory to send sack the next instruction byte. The pre-fetch instruction and queue scheme greatly speeds up processing. The instruction of fetching the next instruction while the current instruction executes is called pipe lining.

(b). Segment Registers : The Bus Interface Unit contains four 16 bit segment registers. They are :

  • Code Segment Register (CS)
  • Stock Segment Register (SS)
  • Extra Segment Register (ES)
  • Data Segment Register (DS)
(c) Instruction Pointer : The instruction pointer register register which holds the address of the next code byte that is to be fetched within the code segment. This register contains the address value which is an offset, because this value must be added to the segment base address contained in CS register to produce the required 20 bit physical address.
EU :  Execution unit of 8086 tells the BIU, where to fetch instruction and data from, decodes instruction and executes instruction. The following  sections describe functional parts of the execution unit. Goes for deciding and interpretation, one byte in the queue becomes empty and subsequently the queue is  updated. The microprocessor does not perform next fetch operation, till at least two bytes of the instruction queue are emptied.

To perform the above operations, the execution unit consists of the following sections :
(a) Instruction Decoder, ALU and control circuitry.
(b) Flag Register.
(c) General Purpose Registers.
(d) Stack Pointer Register.
(e) Other pointer and Index Registers.

(a). Instruction decoder, ALU and control circuitry : The instruction decoder in the EU translate instructions fetched from memory into a series of actions which are further carried out. The Arithmetic and Logic Unit of 8086 is of 16 bits which can add, subtract, AND, OR, XOR, increment, decrements, complement or shift the binary numbers. All internal operations of EU are controlled by control circuitry.

(b). Flag Register : 8086 microprocessor contains one 16 bit flag register(status register). A flag register is flip flop which indicates the status of some conditions produced by the execution of an instruction or controls certain operations of the Execution Unit. In a 16 bit flag register, there are nine active flags. Six of the nine flag bits are used to indicate some conditions produced by an instructions. These six flags are called status flag (conditional flags). The remaining three flag bits in the flag register are used to control certain operations of the processor and are called control flags.

(c). General purpose registers : The execution unit 8086 contains eight general purpose registers labelled as AH, AL, BH, BL, CH, CL, DH and DL as shown below :

15 - 8
7 - 0
AX
AH
AL
BX
BH
BL
CX
CH
CL
DX
DH
DL

(c). Stack pointer register : The stack pointer register SP is a 16 bit register which contains the 16 bit offset address from the start of the stack segment to the memory location where a word was most recently stored on the stack. The stack memory location where a word was most recently stored is called top of the stack.

(e). Other pointer and index registers : In addition to the stack pointer register SP, the EU of the 8086 also contains a 16 bit base register BR. The base register BP contains the 16 bit offset address relative to the stack segment register SS but it is employed in the based addressing mode of 8086.

Register Organisation of 8086 :

8086 Architecture
 

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